1. Field of the Invention
The present invention relates to a display device, and more particularly, to a liquid crystal display (LCD) device and a method of manufacturing an LCD device.
2. Discussion of the Related Art
In general, cathode ray tubes (CRTs) have been commonly used as display devices in televisions and computer monitors because of their ability to display various colors with high luminance. However, CRTs are relatively large and cannot adequately satisfy present demands for display applications that require reduced weight, portability, low power consumption, and increased screen size and resolution. Accordingly, flat panel displays have been developed for use as monitors for computers, spacecraft, and aircraft.
One type of flat panel display that has been developed is the liquid crystal display (LCD) device. The LCD device commonly includes a first substrate, a second substrate, and a liquid crystal sealed between the first and second substrate.
FIG. 1 is a plan view of a first substrate of an LCD device according to the related art. In FIG. 1, a first substrate 1 is divided into an active region A and a pad region P. Within the active region A, a plurality of gate lines G1, G2, . . . , Gn are arranged to cross a plurality of data lines D1, D2, . . . , Dn so that a plurality of pixel regions are defined. A pixel electrode 8 is formed in each pixel region, and a thin film transistor (TFT) (not shown) is formed at each crossing point between the respective gate and data lines. Within the pad region P, a plurality of gate pads Gp1, Gp2, . . . , Gpn and a plurality of data pads Dp1, Dp2, . . . , Dpn are arranged. The gate pads Gp1, Gp2, . . . , Gpn transmit gate signals output from a gate driving IC (not shown) to the gate lines G1, G2, . . . , Gn. The data pads Dp1, Dp2, . . . , Dpn transmit data signals output from a data driving IC (not shown) to the data lines D1, D2, . . . , Dn.
FIG. 2 is a cross sectional view of the LCD device according to the related art taken along I-I′ of FIG. 1. In FIG. 2, the LCD includes a first substrate 1 and a second substrate 2 that are mutually attached to each other to form a single body. A gate electrode 3 is formed on the first substrate 1, and a gate insulating film 4 is formed on an entire surface of the first substrate 1 including the gate electrode 3. A semiconductor layer 5 is formed on a portion of the gate insulating film 4 that corresponds to the gate electrode 3. Source and drain electrodes 6a and 6b are formed at both sides on the semiconductor layer 5. Accordingly, the gate electrode 3, the semiconductor layer 5, and the source/drain electrodes 6a and 6b constitute a TFT. A passivation film 7 is formed on an entire surface of the first substrate 1 including the TFT. A pixel electrode 8, which is connected to the drain electrode 6b, is formed on the passivation film 7, and an alignment film 9a for regular alignment of a liquid crystal is formed on an entire surface of the substrate including the pixel electrode 8
A light-shielding layer 10 is formed on the second substrate 2 to shield any light that leaks from the gate and data lines and the TFT. A color filter layer 11 is formed to oppose the pixel electrode 8 formed on the first substrate 1, and a common electrode 13 made of a transparent material is formed on the color filter layer 11 and the light-shielding layer 10. An alignment film 9b is formed on the common electrode 13, and an overcoat layer 12 may further be formed on the light-shielding layer 10 and the color filter layer 11 to planarize the second substrate 2.
A liquid crystal material layer 15, a spacer 14, and a sealant 16 are formed between the first substrate 1 and the second substrate 2. The liquid crystal material layer 15 possesses an alignment characteristic due to the alignment films 9a and 9b. The spacer is formed of a plastic material and provides a space between opposing surfaces of the first and second substrates 1 and 2. The sealant 16 attaches the first and second substrates 1 and 2 to each other, and seals an outer portion of the active region A to prevent humidity or other substances from entering into the liquid crystal material layer 15. In addition, a driving circuit (not shown) for driving the TFT is connected to the first substrate 1 by a tape carrier package (not shown).
The pad region P of the aforementioned related art LCD will be described in more detail with reference to FIG. 3.
FIG. 3 is a cross sectional view of the LCD device according to the related art taken along II-II′ of FIG. 1. In FIG. 3, a gate pad Gp1 extends from a gate line G1 formed at a pad region on the first substrate 1. A gate insulating film 4 is formed on the gate pad Gp1, the gate line G1, and over an entire surface of the first substrate 1, and a passivation film 7 is formed on the gate insulating film 4 and over an entire surface of the first substrate 1. Then, a contact hole is formed to pass through the passivation film 7 and the gate insulating film 4. A transparent conductive film 8a formed of indium tin oxide (ITO) is formed to electrically interconnect the gate pad Gp1 with a driving circuit (not shown) via the contact hole. The gate pad Gp1 is formed of an opaque metal such as Al, Cr, Mo, Cu, Al alloy, or a multiple layer structure thereof, and the gate insulating film 4 and the passivation film 7 are formed of SiNx.
The gate insulating film 4 and the passivation film 7 are formed by a plasma chemical vapor deposition (CVD) method using a mixed gas of SiH4 and NH3. The contact hole of the gate insulating film 4 and the passivation film 7 are formed by an etching process to connect the gate pad Gp1 with the driving circuit.
FIGS. 4A and 4B show cross sectional views of a gate pad according to the related art during a portion of a manufacturing process.
FIG. 4A is a cross sectional view of a gate pad according to the related art taken along II-II′ of FIG. 1 after a gate insulating film and a passivation film are etched. In FIG. 4A, the gate insulating film 4 and the passivation film 7 are formed on the gate pad Gp1, and then a contact hole is etched.
FIG. 4B is a cross sectional view of a gate pad according to the related art taken along II-II′ of FIG. 1 after a transparent conductive film has been deposited. In FIG. 4B, a transparent conductive film 8a is formed to electrically interconnect the gate pad Gp1 with the driving circuit (not shown). However, the transparent conductive film 8a may not electrically interconnect the gate pad Gp1 to the driving circuit due to excessive etching of the gate insulating film 4. Arrows of FIG. 4B represent portions of the transparent conductive film 8a that may fail to interconnect the gate pad Gp1 with the driving circuit.
FIG. 5 is a scanning electron microscope (SEM) photograph of a gate pad according to the related art taken along II-II′ of FIG. 1. In FIG. 5, the SiNx of the gate insulating film 4 is significantly overetched.